This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2001-384184, filed on Dec. 18, 2001; the entire contents of which are incorporated herein by reference.
1. Field of the Invention
The present invention relates to a semiconductor device and a method of manufacturing the same.
2. Related Background Art
Recently, as the miniaturization of devices advances, MOS transistors including diffusion layer regions (hereinafter also referred to as xe2x80x9cextension regionsxe2x80x9d), of which the impurity concentration is lower than that of source/drain regions, have been proposed. In such a MOS transistor, an extension region, of which the junction depth with a semiconductor substrate or a well is shallow, is required for improving the short channel effect, and an extension region, of which the change in impurity concentration per unit length in the direction of the depth of the semiconductor substrate is considerably large, i.e., the impurity concentration profile in the depth direction of the semiconductor substrate is abrupt, is required to reduce the parasitic resistance (spreading resistance).
When extension regions of source/drain regions are formed by implanting impurities into a semiconductor substrate by the ion implantation method, one way of forming an extension region, of which the junction depth is shallow and of which the impurity concentration profile in the depth direction of the semiconductor substrate is abrupt, is to decrease the acceleration energy at the time of the ion-implantation.
However, if the acceleration energy at the time of the ion-implantation is reduced, especially for a p-channel MOSFET, a problem may arise that the sheet resistance in the extension regions is increased to increase the parasitic resistance, thereby degrading the capability of driving current.
A semiconductor device according to a first aspect of the present invention includes: a gate insulating layer formed on an n-type silicon semiconductor region; a gate electrode formed on the gate insulating layer; a channel region formed immediately below the gate electrode in the semiconductor region; p-type source/drain regions formed at both sides of the channel region in the semiconductor region; p-type diffusion layer regions formed between the channel region and the source/drain regions in the semiconductor region and having a lower impurity concentration than the source/drain regions; first impurity regions formed near surface portions of the diffusion layer regions; and second impurity regions formed in part of the p-type diffusion layer regions and near surface portions of the source/drain regions, the second impurity regions being deeper than the first impurity regions, and the first and second impurity regions containing one element selected from germanium, silicon, gallium, and indium as impurity.
A method of manufacturing a semiconductor device according to a second aspect of the present invention includes: forming a gate electrode via a gate insulating layer on an n-type silicon semiconductor region; forming a first gate sidewall of an insulating material at a side portion of the gate electrode; forming first impurity regions including an amorphous layer at both sides of the first gate sidewall in the semiconductor region through ion-implantation of one element selected from germanium, silicon, gallium, and indium into the semiconductor region using the gate electrode and the first gate sidewall as masks; and after removing the first gate sidewall, forming second impurity regions including an amorphous layer shallower than the amorphous layer of the first impurity regions through ion-implantation of the one element into the semiconductor region using the gate electrode as a mask.